cystech electronics corp. spec. no. : c998e3 issued date : 2016.08.01 revised date : page no. : 1/ 8 mtb2d5n03be3 cystek product specification n-channel enhancement mode power mosfet mtb2d5n03be3 bv dss 30v i d @v gs =10v, t c =25 c 111a(si limit) i d @v gs =10v, t c =25 c features 66a(pkg limit) 17.5a i d @v gs =10v, t a =25 c ? low on resistance ? simple drive requirement ? low gate charge r ds(on) @v gs =10v, i d =30a 3.5 m (typ) r ds(on) @v gs =4.5v, i d =20a ? fast switching characteristic ? rohs compliant package symbol outline ordering information mtb2d5n03be3 to-220 device package shipping MTB2D5N03BE3-0-UB-X to-220 (rohs compliant) 50 pcs/tube, 20 tubes/box, 4 boxes / carton g gate d drain ssource 4.6 m (typ) environment friendly grade : s for rohs compliant products, g for rohs compliant and green compound products g d s packing spec, ub : 50 pcs / tube, 20 tubes/box product rank, zero for no rank products product name
cystech electronics corp. spec. no. : c998e3 issued date : 2016.08.01 revised date : page no. : 2/ 8 mtb2d5n03be3 cystek product specification absolute maximum ratings (t c =25 c) parameter symbol limits unit drain-source voltage (note 1) v ds 30 gate-source voltage v gs 20 v continuous drain current @t c =25 c, v gs =10v(silicon limit) (note 1) 111 continuous drain current @t c =100c, v gs =10v(silicon limit) (note 1) 70 continuous drain current @t c =25 c, v gs =10v(package limit) (note 1) i d 66 continuous drain current @t a =25 c, v gs =10v (note 2) 17.5 continuous drain current @t a =70 c, v gs =10v (note 2) i dsm 14.0 pulsed drain current @ v gs =10v(package limit) i dm 264 avalanche current @ l=0.1mh i as 55 a single pulse avalanche energy @ l=5mh, i d =13 amps, v dd =20v (note 4) e as 422.5 repetitive avalanche energy (note 3) e ar 8 mj t c =25 c (note 1) 83 t c =100c (note 1) p d 33.2 t a =25 c (note 2) 2.1 power dissipation t a =70 c (note 2) p dsm 1.3 w maximum temperature for soldering @ lead at 0.063 in(1.6mm) from case for 10 seconds t l 300 maximum temperature for soldering @ package body for 10 seconds t pkg 260 operating junction and storage temperature tj, tstg -55~+150 c *drain current limited by maximum junction temperature thermal data parameter symbol value unit thermal resistance, junction-to-case, max r jc 1.5 thermal resistance, junction-to-ambient, max (note 2) r ja 60 c/w note : 1 . the power dissipation p d is based on t j(max) =150 c, using junction-to-case thermal resistance, and is more useful in setting the upper di ssipation limit for cases where additional heatsinking is used. 2 . the value of r ja is measured with the device mounted on 1 in 2 fr-4 board with 2 oz. copper, in a still air environment with t a =25 c. the power dissipation p dsm is based on r ja and the maximum allowed junction temperature of 150 c. the value in any given application depends on the user?s specific board design, and the maximum temperature of 175 c may be used if the pcb allows it. 3 . pulse width limited by junction temperature t j(max) =150 c. ratings are based on low frequency and low duty cycles to keep initial t j =25 c. 4. 100% tested by condition of v dd =15v, i d =30a, l=0.1mh, v gs =10v.
cystech electronics corp. spec. no. : c998e3 issued date : 2016.08.01 revised date : page no. : 3/ 8 mtb2d5n03be3 cystek product specification characteristics (tj=25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss 30 - - v v gs =0v, i d =250 a ? bv dss / ? tj - 28 - mv/ c reference to 25c, i d =250 a v gs(th) 1 - 2.5 v v ds = v gs , i d =250 a *g fs - 32.5 - s v ds =10v, i d =30a i gss - - 100 na v gs = 20v - - 1 v ds =30v, v gs =0v i dss - - 5 a v ds =24v, v gs =0v, tj=55 c - 3.5 4.5 v gs =10v, i d =30a *r ds(on) - 4.6 6.0 m v gs =4.5v, i d =20a dynamic *qg - 56 - *qgs - 8.1 - *qgd - 13.5 - nc v dd =15v, i d =30a,v gs =10v *t d(on) - 17.8 - *tr - 19.4 - *t d(off) - 61 - *t f - 14.2 - ns v dd =15v, i d =30a, v gs =10v, r g =3 ciss - 2657 - coss - 478 - crss - 290 - pf v gs =0v, v ds =15v, f=1mhz rg - 1.8 - f=1mhz source-drain diode *i s - - 66 *i sm - - 264 a *v sd - 0.82 1.2 v i s =20a, v gs =0v *trr - 19.8 - ns *qrr - 11.3 - nc v gs =0v, i f =20a, di f /dt=100a/ s *pulse test : pulse width 300 s, duty cycle 2%
cystech electronics corp. spec. no. : c998e3 issued date : 2016.08.01 revised date : page no. : 4/ 8 mtb2d5n03be3 cystek product specification typical characteristics typical output characteristics 0 20 40 60 80 100 120 140 160 180 200 012345 v ds , drain-source voltage(v) i d , drain current (a) 10v, 9v,8v,7v,6v v gs =3v 4v 3 .5v 4.5 v 5 v 6v brekdown voltage vs ambient temperature 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature(c) bv dss , normalized drain-source breakdown voltage i d =250 a, v gs =0v static drain-source on-state resistance vs drain current 1 10 100 0.01 0.1 1 10 100 i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) v gs =10v v gs =4.5v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 024681 i dr , reverse drain current(a) v sd , source-drain voltage(v) 0 tj=25c tj=150c v gs =0v static drain-source on-state resistance vs gate-source voltage 0 20 40 60 80 100 120 140 160 180 200 024681 0 drain-source on-state resistance vs junction tempearture 0 0.4 0.8 1.2 1.6 2 2.4 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature(c) r ds(on) , normalized static drain- source on-state resistance v gs =10v, i d =30a r ds( on) @tj=25c : 3.5m typ. v gs , gate-source voltage(v) r ds(on) , static drain-source on- state resistance(m) i d =30a
cystech electronics corp. spec. no. : c998e3 issued date : 2016.08.01 revised date : page no. : 5/ 8 mtb2d5n03be3 cystek product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 100 1000 10000 0 5 10 15 20 25 30 v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.2 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature(c) v gs(th) , normalized threshold voltage i d =250 a i d =1ma forward transfer admittance vs drain current 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 100 i d , drain current(a) g fs , forward transfer admittance(s) ta=25c pulsed v ds =10v v ds =15v gate charge characteristics 0 2 4 6 8 10 0 102030405060 qg, total gate charge(nc) v gs , gate-source voltage(v) v ds =15v i d =30a maximum safe operating area 0.1 1 10 100 1000 0.1 1 10 100 v ds , drain-source voltage(v) i d , drain current(a) t c =25c, tj=150c v gs =10v, r jc =1.5c/w single pulse dc 100ms r dson limited 10 s 100 s 1ms 10ms maximum drain current vs case temperature 0 20 40 60 80 100 120 25 50 75 100 125 150 175 200 t c , case temperature(c) i d , maximum drain current(a) v gs =10v, r jc =1.5c/w silicon limit package limit
cystech electronics corp. spec. no. : c998e3 issued date : 2016.08.01 revised date : page no. : 6/ 8 mtb2d5n03be3 cystek product specification typical characteristics(cont.) typical transfer characteristics 0 20 40 60 80 100 120 140 160 180 200 012345 v gs , gate-source voltage(v) i d , drain current(a) v ds =10v single pulse power rating, junction to case 0 200 400 600 800 1000 1200 1400 1600 1800 2000 0.0001 0.001 0.01 0.1 1 10 pulse width(s) power (w) t j(max) =150c t c =25c r jc =1.5c/w transient thermal response curves 0.01 0.1 1 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 t 1 , square wave pulse duration(s) r(t), normalized effective transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r jc (t)=r(t)*r jc 2.duty factor, d=t 1 /t 2 3.t jm -t c =p dm *r jc (t) 4.r jc =1.5c/w
cystech electronics corp. spec. no. : c998e3 issued date : 2016.08.01 revised date : page no. : 7/ 8 mtb2d5n03be3 cystek product specification recommended wave soldering condition soldering time product peak temperature pb-free devices 5 +1/-1 seconds 260 +0/-5 c recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 217 c 60-150 seconds 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6c/second max. 6 minutes max. time 25 c to peak temperature 8 minutes max. note : all temperatures refer to topside of the package, measured on the package body surface.
cystech electronics corp. spec. no. : c998e3 issued date : 2016.08.01 revised date : page no. : 8/ 8 mtb2d5n03be3 cystek product specification to-220 dimension *: typical millimeters inches millimeters inches dim min. marking: 4 style: pin 1.gate 2.drain 3.source 4.drain 3-lead to-220 plastic package cystek package code: e3 device name date code 1 2 3 b2d5 n03b min. max. dim min. max. min. max. max. a 4.400 4.600 0.173 0.181 e 2.540* 0.100* a1 2.250 2.550 0.089 0.100 e1 4.980 5.180 0.196 0.204 b 0.710 0.910 0.028 0.036 f 2.650 2.950 0.104 0.116 b1 1.170 1.370 0.046 0.054 h 7.900 8.100 0.311 0.319 c 0.330 0.650 0.013 0.026 h 0.000 0.300 0.000 0.012 c1 1.200 1.400 0.047 0.055 l 12. 900 13.400 0.508 0.528 d 9.910 0.390 0.404 l1 2.850 3.250 0.112 0.128 10.250 e 8.950 9.750 0.352 0.384 v 7/500 ref 0.295 ref e1 12.650 0.498 0.510 3.400 3.800 0.134 0.150 12.950 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing spec ification or packing method, please cont act your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitab le for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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